With continuous development of semiconductor technology, the feature size of semiconductor device s gradually decreases. The reduction of key dimensions means that more transistors can be arranged on a single chip. In the meantime, the decrease in the feature size also provides challenges in the semiconductor fabrication process.
On a semiconductor chip, different transistors often have different threshold voltages. In order to tune the threshold voltage of a transistor, the semiconductor fabrication technology introduces a work function layer between the gate dielectric layer and the gate electrode when forming the transistor. Depending on the properties and characteristics of the introduced work function layer, such as the material, the thickness, etc. the work function layer may be able to adjust the work function of the transistor, and thus adjust the threshold voltage of the transistor. As such, the formation process for the transistor may be more complicated.
In current technology, using a high-k dielectric layer to form the gate dielectric layer and using a metal gate to form the gate electrode, i.e. using the high-k metal gate (HKMG) technique, has become a core technique to reduce the dimensions of semiconductor devices. Specifically, HKMG fabricated by a gate-last process demonstrates a number of advantages, such as lower energy consumption, smaller leakage current, stable high-frequency performance, etc., and thus has gradually become the semiconductor industry's favor.
However, because of the complexity of the gate-last process and the different requirements on the threshold voltages of different devices formed on the same chip, the fabrication methods for existing semiconductor structures are very complicated. The disclosed semiconductor structures and fabrication methods thereof are directed to solve one or more problems set forth above and other problems in the art.